
#clock
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS33} [get_ports clk]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk]
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN V17} [get_ports clk_o]

#reset
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS33} [get_ports reset_n]


#LED
set_property PACKAGE_PIN L8 [get_ports {led[0]}]
set_property PACKAGE_PIN H9 [get_ports {led[1]}]
set_property PACKAGE_PIN G9 [get_ports {led[2]}]
set_property PACKAGE_PIN K8 [get_ports {led[3]}]
set_property PACKAGE_PIN H8 [get_ports {led[4]}]
set_property PACKAGE_PIN F8 [get_ports {led[5]}]
set_property PACKAGE_PIN G8 [get_ports {led[6]}]
set_property PACKAGE_PIN F7 [get_ports {led[7]}]
set_property PACKAGE_PIN A5 [get_ports {led[8]}]
set_property PACKAGE_PIN G7 [get_ports {led[9]}]
set_property PACKAGE_PIN A4 [get_ports {led[10]}]
set_property PACKAGE_PIN D6 [get_ports {led[11]}]
set_property PACKAGE_PIN J19 [get_ports {led[12]}]
set_property PACKAGE_PIN J20 [get_ports {led[13]}]
set_property PACKAGE_PIN J15 [get_ports {led[14]}]
set_property PACKAGE_PIN J14 [get_ports {led[15]}]

#led_rg 0/1
set_property PACKAGE_PIN L18 [get_ports {led_rg0[0]}]
set_property PACKAGE_PIN L17 [get_ports {led_rg0[1]}]
set_property PACKAGE_PIN K17 [get_ports {led_rg1[0]}]
set_property PACKAGE_PIN K16 [get_ports {led_rg1[1]}]

#NUM
set_property PACKAGE_PIN E25 [get_ports {num_csn[7]}]
set_property PACKAGE_PIN E23 [get_ports {num_csn[6]}]
set_property PACKAGE_PIN G20 [get_ports {num_csn[5]}]
set_property PACKAGE_PIN F22 [get_ports {num_csn[4]}]
set_property PACKAGE_PIN F23 [get_ports {num_csn[3]}]
set_property PACKAGE_PIN F24 [get_ports {num_csn[2]}]
set_property PACKAGE_PIN F25 [get_ports {num_csn[1]}]
set_property PACKAGE_PIN E26 [get_ports {num_csn[0]}]

set_property PACKAGE_PIN D26 [get_ports {num_a_g[0]}]
set_property PACKAGE_PIN G24 [get_ports {num_a_g[1]}]
set_property PACKAGE_PIN H24 [get_ports {num_a_g[2]}]
set_property PACKAGE_PIN G25 [get_ports {num_a_g[3]}]
set_property PACKAGE_PIN H22 [get_ports {num_a_g[4]}]
set_property PACKAGE_PIN H21 [get_ports {num_a_g[5]}]
set_property PACKAGE_PIN G22 [get_ports {num_a_g[6]}]
#set_property PACKAGE_PIN G21 :DP

#switch
set_property PACKAGE_PIN Y16 [get_ports {switch[7]}]
set_property PACKAGE_PIN Y15 [get_ports {switch[6]}]
set_property PACKAGE_PIN AC18 [get_ports {switch[5]}]
set_property PACKAGE_PIN AD18 [get_ports {switch[4]}]
set_property PACKAGE_PIN AB16 [get_ports {switch[3]}]
set_property PACKAGE_PIN AD17 [get_ports {switch[2]}]
set_property PACKAGE_PIN AC17 [get_ports {switch[1]}]
set_property PACKAGE_PIN AC16 [get_ports {switch[0]}]

#btn_key
set_property PACKAGE_PIN AC23 [get_ports {btn_key_col[0]}]
set_property PACKAGE_PIN W14 [get_ports {btn_key_col[1]}]
set_property PACKAGE_PIN AC22 [get_ports {btn_key_col[2]}]
set_property PACKAGE_PIN AB21 [get_ports {btn_key_col[3]}]
set_property PACKAGE_PIN AE18 [get_ports {btn_key_row[0]}]
set_property PACKAGE_PIN W15 [get_ports {btn_key_row[1]}]
set_property PACKAGE_PIN AF18 [get_ports {btn_key_row[2]}]
set_property PACKAGE_PIN AE17 [get_ports {btn_key_row[3]}]

#btn_step
set_property PACKAGE_PIN AC21 [get_ports {btn_step[0]}]
set_property PACKAGE_PIN AA20 [get_ports {btn_step[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {led[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_rg0[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_rg1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {num_a_g[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {num_csn[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn_key_col[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn_key_row[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn_step[*]}]

#uart
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN E6} [get_ports UART_TX]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN D5} [get_ports UART_RX]

set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN M14} [get_ports LCD_UART_TX]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN L14} [get_ports LCD_UART_RX]
#GPIO
#SPI FLASH
# sck
set_property -dict {PACKAGE_PIN M25 IOSTANDARD LVCMOS33} [get_ports {GPIO[0]}]
# cs
set_property -dict {PACKAGE_PIN L24 IOSTANDARD LVCMOS33} [get_ports {GPIO[1]}]
# dq0(mosi)
set_property -dict {PACKAGE_PIN K25 IOSTANDARD LVCMOS33} [get_ports {GPIO[2]}]
# dq1(miso)
set_property -dict {PACKAGE_PIN K26 IOSTANDARD LVCMOS33} [get_ports {GPIO[3]}]
# dp2 悬空
set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports {GPIO[4]}]
# dq3 悬空
set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS33} [get_ports {GPIO[5]}]

#I2C
# FPGA_EXT0_IO0 scl
set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS33} [get_ports {GPIO[6]}]
# FPGA_EXT0_IO1 sda
set_property -dict {PACKAGE_PIN N21 IOSTANDARD LVCMOS33} [get_ports {GPIO[7]}]

#others
# FPGA_EXT_IO0
set_property -dict {PACKAGE_PIN U26 IOSTANDARD LVCMOS33} [get_ports {GPIO[8]}]
# FPGA_EXT_IO1
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS33} [get_ports {GPIO[9]}]
# FPGA_EXT0_IO2 ~ FPGA_EXT0_IO24
set_property -dict {PACKAGE_PIN R26 IOSTANDARD LVCMOS33} [get_ports {GPIO[10]}]
set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS33} [get_ports {GPIO[11]}]
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS33} [get_ports {GPIO[12]}]
set_property -dict {PACKAGE_PIN P23 IOSTANDARD LVCMOS33} [get_ports {GPIO[13]}]
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS33} [get_ports {GPIO[14]}]
set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS33} [get_ports {GPIO[15]}]
set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS33} [get_ports {GPIO[16]}]
set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS33} [get_ports {GPIO[17]}]
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVCMOS33} [get_ports {GPIO[18]}]
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVCMOS33} [get_ports {GPIO[19]}]
set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports {GPIO[20]}]
set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports {GPIO[21]}]
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS33} [get_ports {GPIO[22]}]
set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS33} [get_ports {GPIO[23]}]
set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS33} [get_ports {GPIO[24]}]
set_property -dict {PACKAGE_PIN L20 IOSTANDARD LVCMOS33} [get_ports {GPIO[25]}]
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS33} [get_ports {GPIO[26]}]
set_property -dict {PACKAGE_PIN L25 IOSTANDARD LVCMOS33} [get_ports {GPIO[27]}]
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS33} [get_ports {GPIO[28]}]
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS33} [get_ports {GPIO[29]}]
set_property -dict {PACKAGE_PIN N24 IOSTANDARD LVCMOS33} [get_ports {GPIO[30]}]
set_property -dict {PACKAGE_PIN N23 IOSTANDARD LVCMOS33} [get_ports {GPIO[31]}]

set_property -dict {PACKAGE_PIN C1 IOSTANDARD LVCMOS33} [get_ports {dram_addr[0]}]
set_property -dict {PACKAGE_PIN B1 IOSTANDARD LVCMOS33} [get_ports {dram_addr[1]}]
set_property -dict {PACKAGE_PIN A2 IOSTANDARD LVCMOS33} [get_ports {dram_addr[2]}]
set_property -dict {PACKAGE_PIN A3 IOSTANDARD LVCMOS33} [get_ports {dram_addr[3]}]
set_property -dict {PACKAGE_PIN B2 IOSTANDARD LVCMOS33} [get_ports {dram_addr[4]}]
set_property -dict {PACKAGE_PIN C2 IOSTANDARD LVCMOS33} [get_ports {dram_addr[5]}]
set_property -dict {PACKAGE_PIN F2 IOSTANDARD LVCMOS33} [get_ports {dram_addr[6]}]
set_property -dict {PACKAGE_PIN E2 IOSTANDARD LVCMOS33} [get_ports {dram_addr[7]}]
set_property -dict {PACKAGE_PIN E1 IOSTANDARD LVCMOS33} [get_ports {dram_addr[8]}]
set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS33} [get_ports {dram_addr[9]}]
set_property -dict {PACKAGE_PIN D1 IOSTANDARD LVCMOS33} [get_ports {dram_addr[10]}]
set_property -dict {PACKAGE_PIN G1 IOSTANDARD LVCMOS33} [get_ports {dram_addr[11]}]
set_property -dict {PACKAGE_PIN H3 IOSTANDARD LVCMOS33} [get_ports {dram_addr[12]}]
set_property -dict {PACKAGE_PIN L3 IOSTANDARD LVCMOS33} [get_ports {dram_ba[0]}]
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {dram_ba[1]}]
set_property -dict {PACKAGE_PIN L2 IOSTANDARD LVCMOS33} [get_ports dram_cas_n]
set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports dram_cke]
set_property -dict {PACKAGE_PIN N3 IOSTANDARD LVCMOS33} [get_ports dram_clk]
set_property -dict {PACKAGE_PIN M2 IOSTANDARD LVCMOS33} [get_ports {dram_cs_n[0]}]
set_property -dict {PACKAGE_PIN J1 IOSTANDARD LVCMOS33} [get_ports {dram_cs_n[1]}]
set_property -dict {PACKAGE_PIN N2 IOSTANDARD LVCMOS33} [get_ports dram_ras_n]
set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports dram_we_n]
set_property -dict {PACKAGE_PIN L4 IOSTANDARD LVCMOS33} [get_ports {dram_dq[0]}]
set_property -dict {PACKAGE_PIN L5 IOSTANDARD LVCMOS33} [get_ports {dram_dq[1]}]
set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {dram_dq[2]}]
set_property -dict {PACKAGE_PIN K5 IOSTANDARD LVCMOS33} [get_ports {dram_dq[3]}]
set_property -dict {PACKAGE_PIN R8 IOSTANDARD LVCMOS33} [get_ports {dram_dq[4]}]
set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS33} [get_ports {dram_dq[5]}]
set_property -dict {PACKAGE_PIN T8 IOSTANDARD LVCMOS33} [get_ports {dram_dq[6]}]
set_property -dict {PACKAGE_PIN T7 IOSTANDARD LVCMOS33} [get_ports {dram_dq[7]}]
set_property -dict {PACKAGE_PIN R6 IOSTANDARD LVCMOS33} [get_ports {dram_dq[8]}]
set_property -dict {PACKAGE_PIN R7 IOSTANDARD LVCMOS33} [get_ports {dram_dq[9]}]
set_property -dict {PACKAGE_PIN N6 IOSTANDARD LVCMOS33} [get_ports {dram_dq[10]}]
set_property -dict {PACKAGE_PIN M6 IOSTANDARD LVCMOS33} [get_ports {dram_dq[11]}]
set_property -dict {PACKAGE_PIN M5 IOSTANDARD LVCMOS33} [get_ports {dram_dq[12]}]
set_property -dict {PACKAGE_PIN M4 IOSTANDARD LVCMOS33} [get_ports {dram_dq[13]}]
set_property -dict {PACKAGE_PIN M7 IOSTANDARD LVCMOS33} [get_ports {dram_dq[14]}]
set_property -dict {PACKAGE_PIN L7 IOSTANDARD LVCMOS33} [get_ports {dram_dq[15]}]
set_property -dict {PACKAGE_PIN P6 IOSTANDARD LVCMOS33} [get_ports {dram_dq[16]}]
set_property -dict {PACKAGE_PIN R5 IOSTANDARD LVCMOS33} [get_ports {dram_dq[17]}]
set_property -dict {PACKAGE_PIN R3 IOSTANDARD LVCMOS33} [get_ports {dram_dq[18]}]
set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {dram_dq[19]}]
set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {dram_dq[20]}]
set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {dram_dq[21]}]
set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {dram_dq[22]}]
set_property -dict {PACKAGE_PIN P1 IOSTANDARD LVCMOS33} [get_ports {dram_dq[23]}]
set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS33} [get_ports {dram_dq[24]}]
set_property -dict {PACKAGE_PIN T5 IOSTANDARD LVCMOS33} [get_ports {dram_dq[25]}]
set_property -dict {PACKAGE_PIN T4 IOSTANDARD LVCMOS33} [get_ports {dram_dq[26]}]
set_property -dict {PACKAGE_PIN T3 IOSTANDARD LVCMOS33} [get_ports {dram_dq[27]}]
set_property -dict {PACKAGE_PIN T2 IOSTANDARD LVCMOS33} [get_ports {dram_dq[28]}]
set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports {dram_dq[29]}]
set_property -dict {PACKAGE_PIN U2 IOSTANDARD LVCMOS33} [get_ports {dram_dq[30]}]
set_property -dict {PACKAGE_PIN R2 IOSTANDARD LVCMOS33} [get_ports {dram_dq[31]}]
set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {dram_dqml[0]}]
set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {dram_dqml[1]}]
set_property -dict {PACKAGE_PIN N7 IOSTANDARD LVCMOS33} [get_ports {dram_dqmh[0]}]
set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports {dram_dqmh[1]}]

create_generated_clock -name ddr_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2]
#create_generated_clock -name ddr_clk -source [get_pins ddr3.u_axi_wrap_ddr/u_sdram/ODDR_inst/C] #                            -multiply_by 1 [get_pins ddr3.u_axi_wrap_ddr/u_sdram/ODDR_inst/Q]
create_generated_clock -name dram_clk -source [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT2] \
                        -divide_by 1 [get_ports dram_clk]
set_input_delay  -clock dram_clk -max 2.500  [get_ports {dram_dq[*]}]
set_output_delay -clock dram_clk -min -0.800 [get_ports {dram_dq[*]}]
set_output_delay -clock dram_clk -min -0.800 [get_ports {dram_addr[*]}]
set_output_delay -clock dram_clk -min -0.800 [get_ports {dram_dqml[*]}]
set_output_delay -clock dram_clk -min -0.800 [get_ports {dram_dqmh[*]}]
set_output_delay -clock dram_clk -min -0.800 [get_ports dram_we_n]
set_output_delay -clock dram_clk -min -0.800 [get_ports dram_ras_n]
set_output_delay -clock dram_clk -min -0.800 [get_ports dram_cas_n]
set_output_delay -clock dram_clk -min -0.800 [get_ports {dram_cs_n[*]}]
set_output_delay -clock dram_clk -min -0.800 [get_ports dram_cke]

set_output_delay -clock dram_clk -max 1.500 [get_ports {dram_dq[*]}]
set_output_delay -clock dram_clk -max 1.500 [get_ports {dram_addr[*]}]
set_output_delay -clock dram_clk -max 1.500 [get_ports {dram_dqml[*]}]
set_output_delay -clock dram_clk -max 1.500 [get_ports {dram_dqmh[*]}]
set_output_delay -clock dram_clk -max 1.500 [get_ports dram_we_n]
set_output_delay -clock dram_clk -max 1.500 [get_ports dram_ras_n]
set_output_delay -clock dram_clk -max 1.500 [get_ports dram_cas_n]
set_output_delay -clock dram_clk -max 1.500 [get_ports {dram_cs_n[*]}]

create_generated_clock -name cpu_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT0]
create_generated_clock -name sys_clk [get_pins pll_clk.u_clk_pll/inst/plle2_adv_inst/CLKOUT1]

set_clock_groups -asynchronous -group [get_clocks cpu_clk] -group [get_clocks sys_clk] -group [get_clocks ddr_clk]
